1. Field of the Invention
The present invention relates to a semiconductor memory device technology. More specifically, the present invention relates to nonvolatile memory devices having a split gate structure and a fabrication method thereof.
2. Description of the Related Art
Flash memory, which is capable of retaining stored data without continued supply of electrical power, typically has a stacked gate structure including a floating gate and a control gate. The floating gate, which is between the control gate and the semiconductor substrate, is isolated by an insulating oxide layer. The flash memory device may be classified, according to its cell array structure, into NOR flash and NAND flash types. The NAND flash has higher integration and is suitable for use in electronic devices requiring high storage capacity. The NOR flash memory allows for higher speed operation and random access to the memory cells, but it generally uses space for the each of memory cells for interconnection to a bit line. NOR flash memory also generally has a relatively low integrity.
The NOR flash memory devices have a plurality of memory cells arrayed in row and column directions. Memory cells placed in a row direction are connected in parallel to bit lines, while memory cells placed in a column direction are connected in parallel to word lines. As the memory cells are connected to parallel bit lines, when the cell transistor's threshold voltage becomes lower than the voltage applied to the word line of non-selected memory cells (typically “0” voltage), current may flow between the source and drain regions, which causes an error (e.g., false recognition of certain cells being turned-on). For overcoming this problem, split gate type nonvolatile memory devices are developed.
In the meanwhile, the stacked gate nonvolatile memory device structures may also be divided into FLOTOX (floating-gate-tunnel-oxide) flash memory; and SONOS (silicon-oxide-nitride-oxide-silicon) devices, having multiple oxide and/or dielectric layers and a structure similar to a conventional metal oxide semiconductor (MOS) transistor. The SONOS device includes a charge trapping dielectric layer, which stores charges in deep level trap, thereby providing reliability and allowing erasing and programming operations at a low voltage.
FIGS. 1 to 3 are cross-sectional views for illustrating conventional split gate type nonvolatile memory device.
Referring to FIG. 1, an isolation region (not shown) for defining an active region 11 where microcircuit elements such as memory cells are to be fabricated, a charge trapping layer, a first conducting layer and a capping layer are formed in and on a semiconductor substrate 10. The charge trapping layer is, in the case of SONOS devices, an insulating layer that is interposed between tunnel oxide and blocking oxide layers and has high trap density (typically, an oxide-nitride interface in a silicon oxide-silicon nitride-silicon oxide (ONO) stack). A silicon layer (e.g., polysilicon) may be formed thereon (e.g., to function as a control gate) and a silicon nitride layer (e.g., to function as a hard mask) are generally formed on the ONO stack.
By successively patterning the capping layer, the first conducting layer and the charge trapping layer, the first conducting pattern 16 on a charge trapping layer 14 on the active region 11, and oxide pattern 18 and nitride pattern 20 on the first conducting layer 16 may be obtained.
Referring to FIG. 2, spacer insulating layers 22 are formed on sidewalls of the first conducting layer 16, and a gate oxide layer 24 is formed on the active region. A conformal second conducting layer 26 (e.g., polysilicon) is formed on the gate oxide layer 24. At this stage, the second conducting layer 26 has a groove “G” between the first conducting patterns 16. Then, a photoresist pattern 28 is formed on the second conducting layer 26.
Referring to FIG. 3, the second conducting layer 26 is patterned using the photoresist pattern 28 as an etch mask to expose portions of the active region between neighboring first conducting patterns 16. The removal of the second conducting layer 26 is done by anisotropic etching. However, sidewalls of the second conducting layer 26, which are formed at the groove “G” may not be properly etched because polymers or byproducts may accumulate thereon during the anisotropic etching process. As a result, electrically conductive stringers 30 remain on the substrate surface after the second conducting layer 26 is etched to expose the gate oxide layer 24.
With the stringers 30 remaining on the substrate, subsequent silicidation is hindered, which leads to an increase in resistance of the active region and of contact resistance, and the stringers 30 may produce particles in following processing steps.
For avoiding the stringer problem, one may consider increasing a time for overetching the second conducting layer 26. In this case, however, the silicon oxide layer formed on the substrate may be removed and the substrate can be damaged. Further, when the topology of the second conducting layer 26 is reduced for alleviating the stringer problem, the first conducting pattern 16 and capping patterns 18 and 20 are generally made thinner. However, this causes an increase in the resistance of the first conducting layer 16. Furthermore, the thinner capping patterns 18 and 20 may increase parasitic capacitance between the first and second conducting layers 16 and 26.